Homepage > Projects > Architecture for Big Data & Machine Learning

Architecture for Big Data & Machine Learning

Intel Domain Leader : Debbie Marr

Big Data Computing results in huge (and costly) energy consumption. Computing Technology energy is dominated by data movement. The research aims at new paradigms in handling data movements in Big Data environment consisting of minimizing data movement, moving the computing closer to the data, accelerating the computing, and exploiting more effective novel memory technologies.

The projects 

Optimized IA for Big Data & Machine Learning Workloads

Academia Researcher(s):

Participating Student(s)

Research Project Summary:
 This research project will explore break-through performance and energy efficiency for a big data analytics platform addressing four major storage and computation challenges:

  1. Data movement within/across nodes, and what/where computation should be placed in the storage hierarchy,
  2. Accelerators for Big Data
  3. Application and usage of new memory technologies such as Memristors within and across nodes.
  4. Define a new Prediction Environment based on Semantic Locality and context-based using Reinforcement Learning applicable to Big Data (both as a tool and Apps enhancements.

 

Uri Weiser –  Publications

  • T. Morad; G. Shomron; M. Erez; A. Kolodny; U. Weiser, “Optimizing Read-Once Data Flow in Big-Data Applications” in IEEE Computer Architecture Letters , vol.PP, no.99, pp.1-1
  •  Tomer Morad, Noam Shalev, Idit Keidar, Avinoam Kolodny, Uri Weiser, “Energy efficient task scheduling”

Ran Ginosar – Publications

Oded Schwartz – Publications

  • Grey Ballard, Alex Druinsky, Nicholas Knight, Oded Schwartz “Hypergraph Partitioning for Sparse Matrix-Matrix Multiplication” arXiv.org > cs > arXiv:1603.05627
  • Ballard, G., Druinsky, A., Knight, N. and Schwartz, O., Hypergraph Partitioning for Sparse Matrix-Matrix Multiplication, Submitted to SIMAX, 2016 – submitted
  • Ballard, G., Benson, A.R., Druinsky, A., Lipshitz, B. and Schwartz, O., Improving the numerical stability of fast matrix multiplication algorithms. Submitted to SIMAX, 2016 – submitted
  • Azad, A., Ballard, G., Buluc, A., Demmel, J., Grigori, L., Schwartz, O., Toledo, S. and Williams, S., 2015. Exploiting Multiple Levels of Parallelism in Sparse Matrix-Matrix Multiplication. Submitted, 2016 – submitted

Yoav Etzion – Publications

Memory Intensive Architectures

Academia Researcher(s):

Participating Student(s) 

Research Project Summary:
 Our research objective is to leverage emerging Non-Volatile Memory (NVM) technologies to increase computing throughput without increasing energy consumption. The research is broad and not necessarily related to a specific emerging NVM technology. Previously, we proposed continuous flow multithreading (CFMT), a multithreaded microarchitecture, where multistate registers are embedded in the pipeline to store the states of multiple threads. CFMT increases the performance to energy of the processor by 42% on average. Additionally, we proposed different circuits for computation within memory and for integration with CMOS logic gates. In this research, we plan to develop novel memory-intensive architectures. These architectures are based on integration of emerging NVM with CMOS and include processor microarchitectures, branch predictors, and utilizing emerging NVM at all levels of the memory hierarchy. We plan to develop and design new device models, circuits, and architectures for memory-intensive machines. Additional microarchitectures for multithreaded processors that further enhance the performance/energy ratio will be developed, as well as additional beneficial applications to multistate registers.

Shahar Kvatinsky – Publications

  • R. Patel, S. Kvatinsky, A. Kolodny, and E. G. Friedman, “STT-MRAM Based Multistate Register.” Integration, the VLSI Journal (submitted)
  • N. Talati, S. Gupta, P. Mane, and S. Kvatinsky, “Logic Design within Memristive Memories Using Memristor Aided loGIC (MAGIC).” IEEE Transactions on Nanotechnology (conditionally accepted)
  • Y. Cassuto, S. Kvatinsky, and E. Yaakobi, “Information-Theoretic Sneak Path Mitigation in Memristor Crossbar Arrays” IEEE International Symposium on Information Theory  2016 (accepted)
  • S. Greshnikov, E. Rosenthal, D. Soudry, and S. Kvatinsky, “A Fully Analog Memristor-Based Multilayer Neural Network with Online Backpropagation Training.” IEEE International Conference on Circuits and Systems (accepted)
  • L. Yavits, S. Kvatinsky, A. Morad and R. Ginosar. “Resistive Associative Processor.”  in IEEE Computer Architecture Letters, vol. 14, no. 2, pp. 148-151, July-Dec. 1 2015. **selected as one of the best papers from IEEE Computer Architecture Letters in 2015
  • Amir Morad, Leonid Yavits, Shahar Kvatinsky and Ran Ginosar. “Resistive GP-SIMD processing-in-memory.” ACM Transactions on Architecture and Code Optimization (TACO)12.4 (2016): 57.

Avinoam Kolodny – Publications

Eby Friedman – Publications

  • A. Ciprut and E. G. Friedman, “Design Models of Resistive Crossbar Arrays with Selector Devices,” Proceedings of the IEEE Symposium on Circuits and Systems, May 2016.